The present invention relates to a semiconductor memory device and a method for writing to the semiconductor memory device, more specifically a semiconductor memory device for memorizing information by storing charges and a method for writing to the semiconductor memory device.
As rewritable nonvolatile semiconductor memory devices are generally known EEPROM, flash EEPROMs, etc., which memorize information by storing charges in the floating gates. For programming in these semiconductor memory devices, charges are injected into the floating gates to thereby write information, and charges stored in the floating gates are extracted to thereby erase information.
The general programming method for the conventional semiconductor memory devices will be explained with reference to FIGS. 14A to 17.
FIG. 14A show one example of applied voltages upon writing. FIG. 14B shows one example of applied voltages upon erasing.
An n-well 202 is formed in p-type semiconductor substrate 200. In the n-well 202, p-well 204 is formed. In the p-well 204, a memory cell transistor including a floating gate 206 as the charge storage layer, a control gate 208 connected to a word line (WL), a source diffused region 210 connected to a source line (SL) and a drain diffused region 212 connected to a bit line (BL) is formed.
When memory information is written to the memory cell transistor, as shown in FIG. 14A, 5 V is applied to the drain diffused region 212 via the bit line (BL), 10 V is applied to the control gate 208 via the word line (WL), the source diffused region 210 is grounded via the source line (SL), and the p-well is grounded. Thus, a current flows between the source diffused region 210 and the drain diffused region 212 to thereby generate hot electrons, and a part of the hot electrons are injected into the floating gate 206. Negative charges (electrons) are injected into the floating gate 206, whereby the threshold voltage Vt of the memory cell transistor becomes high. This state is called program-state.
When information memorized in the memory cell transistor is erased, as shown in FIG. 4B, −10 V is applied to the word line WL and 10 V to the n-well 202 and the p-well 204, and the source diffused region 210 and the drain diffused region 212 are floating. Thus, a high voltage is applied to the tunnel insulating film formed between the floating gate 206 and the p-well 204, whereby electrons stored in the floating gate 206 are extracted to the p-well 204 due to the tunneling phenomenon. When electrons stored in the floating gate 206 are extracted, the threshold voltage Vt of the memory cell transistor becomes low. This state is called erase-state.
FIG. 15 shows one example of applied voltages upon reading information.
When information memorized in the memory cells is read, a voltage of, e.g., 5 V is applied to the word line (WL1) connected to the memory cell transistor MC to be read (selected), voltages of the word lines (WL0, WL2, WL3, . . . ) other than the selected word line (WL1) are, e.g., 0 V (un-selected). A voltage of, e.g., 0.5 V is applied to the bit line (BL1) connected to the memory cell transistor MC to be read (selected), and the other bit lines (BL0, BL2, BL3, . . . ) are floating (un-selected). The source line (SL) connected to the source diffused region 210 of the respective memory cell transistors, and the p-well 204 is grounded. Corresponding to a current flowing in the bit line (BL1) connected to the memory cell transistor MC to be read, when the current is higher than a reference value, the memory cell transistor is judged to be in the erase-state, and when the current is lower, the memory cell transistor MC is judged to be in the program-state.
Accordingly, a memory cell in the program-state is required only to flow no current irrespective of selected or un-selected. On the other hand, a memory cell in the erase-state must flow a large current to be judged as erase-state when selected (WL=5 V). However, if the memory cell in the erase-state flows a current even when un-selected (WL=0 V), the current flows in the selected bit line through the un-selected cells although the selected memory cell is in the program-state and information cannot be correctly read. In order to prevent this, it is necessary that no current should flow when the cell is un-selected (WL=0 V).
FIG. 16 schematically shows the distribution of the threshold voltage Vt of memory cell transistors. As described above, in the program-state the memory cells are required to flow no current irrespective of selected or un-selected and may have threshold voltages larger than a certain value (VT3 in FIG. 16). On the other hand, in the erase-state the memory cells must satisfy two restrictions that the memory cells flow a large current when selected and must flow no current when un-selected. The threshold voltage must be not more than a certain value (VT2) and not less than a certain value (VT1).
Generally, the writing and erasing characteristics of the memory cells cannot be prevented from fluctuations, and as shown in FIG. 16, the threshold voltages Vt of the program-state and the erase-state have fluctuations in the memory cell array. Especially the fluctuations of the erase-state are larger than the fluctuations of the program-state, and after the erase by the tunnel current, some memory cells have threshold voltages of less than VT1. Such cells having threshold voltages of less than VT1 are called over erase cells, and a programming, which is called write-back, to increase the threshold voltage after the erase is required.
In the write-back programming after the erase, 0 voltage, for example, is applied to the word lines (WL), 5 V is applied to the bit lines (BL), and the source line (SL) and the p-well 104 are grounded, whereby light writing is performed. This write-back programming is called a self-convergent programming. The write-back programming after the erase is detailed in, e.g., Reference 1 (Japanese published unexamined patent application No. 2000-268586) and Reference 2 (Japanese published unexamined patent application No. 2000-306390).
FIG. 17 shows one example of the applied voltages in the write-back operation.
In the write-back programming, 5 V, for example, is applied to a selected bit Line (BL1), and the other bit lines (BL0, BL2, BL3, . . . ) are floating. All the word lines (WL0, WL1, WL2, WL3, . . . ), the source line (SL) connected to the source diffused region 210 of the respective memory cell transistors, and the p-well 204 thereof are grounded. Thus, the writing is made in cells connected to the selected bit line (BL) and having low threshold voltages Vt at which currents flow even with 0 V applied to the word lines. The write-back programming is executed for each bit line.
As described above, as a voltage used in writing in the memory cell transistors, a high voltage of 5 V, which is higher than the voltage of the power supply, is required. To this end, a pumping circuit for generating such high voltage is provided in a chip, and the high voltage generated by the pumping circuit is used in the programming for the memory cell transistors. The pumping circuit is described in, e.g., Reference 3 (Japanese published unexamined patent application No. Hei 06-062562) and Reference 4 (Japanese published unexamined patent application No. 2004-297922).